… As an alternative, Beigne and Vivet designed a synchronous-asynchronous FIFO based
on the bisynchronous classical FIFO design using gray code, for the specific case of an …

3D Sequential Integration (3DSI) with ultra-small 3D contact pitch (<100nm) offers new 3D
partitioning options at fine granularities. This paper reviews potential applications ranging …

The demands of scalable, low latency and power efficient system-on-chip interconnect cannot
only be satisfied by point-to-point or shared-bus interconnects. In this paper, we propose a …

… -hopping scheme, we chose a P-type SCCMOS power switch on the TRX-OFDM unit since
the supply voltages can go as low as 0.8 V. It has been shown in [8] that a compromise has to …

Requiring more bandwidth at reasonable power consumption, new communication infrastructures
must provide adequate solutions to guarantee performance during physical integration…

In the context of high-performance computing, the integration of more computing capabilities
with generic cores or dedicated accelerators for artificial intelligence (AI) application is …

… Vivet, and F. Robin, “A design framework for asynchronous/synchronous circuits based on
CHP … Renaudin, and P. Vivet, “A contactless Smart-Card chip based on an asynchronous 8-bit …

In this paper, we propose the design of on-chip and off-chip interfaces adapted to a globally
asynchronous locally synchronous (GALS) network-on-chip (NoC) architecture. The …

A MIMO 3GPP-LTE digital baseband chip based on a heterogeneous 3 × 5 array NoC using
3.2 GOPS/50 mW programmable VLIW cores is presented. It features less than 10 ¿s run-…

In the context of high-performance computing and big-data applications, the quest for
performance requires modular, scalable, energy-efficient, low-cost manycore systems. Partitioning …